Imagery from the current Phase/Hassy/Pentax MF sensor is a couple of years old, meaning that was the point when it was finalized for production, and the followup has doubtless already been prototyped at this point.
Edmund, it sounds like you know a lot about the sensor development cycles, and, surprisingly to me, it seems like they're as long as microprocessor development cycles. Can you answer a few questions for me?
Do new sensor designs typically proceed in lockstep with new process design and feature-size changes, or are sensors usually designed for an already-debugged process?
I know we refer to the dominant image capture technology as CMOS, but, since there are on-chip ADCs, is it really not pure CMOS, but a variation on BiCMOS?
What is the process-limited feature size of state-of-the-art sensors? Yes, I know that, these days, there's a lot of debate about feature size metrics that seemed so clear at a couple of hundred nanometers, but an approximate answer would be useful.
Are the current advances in performance that we're seeing from Sony coming mostly from new processes, or from innovative circuit design? Yes, the question is too broad, but any insight would be useful.
Where do the sensor design engineers usually publish? I see some papers at ISSCC, which used to be, and may still be, the go to conference for microprocessors and memory. Is tehre a better place to look?
In your answer, you might consider the following. I am not a semiconductor designer, but started using ICs in 1963 with tricky-to-use DCTL. I have managed groups that designed a couple of dozen ASICs, though, so I know enough about semiconductor design to get me in trouble.
Thanks for any help you can give.
Jim
