Can full well capacity be maintained while shrinking pixel size?

[ErikKaffehr]

Hi,

I'm shooting 24.6 MP full frame with a CMOS sensor. With aggressive sharpening I see jaggies on edges. Would I have significantly higher resolution those jaggies would probably go away. That would be oversampling but yield better edges.


So I see benefits of increasing resolution. The problem is that when resolution goes up FWC (Full Well Capacity) goes down. What I don't know if this is law of nature or if is possible to make the pixel spacing smaller and maintain FWC? It may be possible by increasing the physical fill factor or by using better dielectrics?

Best regards
Erik

[Bart_van_der_Wolf]

So I see benefits of increasing resolution. The problem is that when resolution goes up FWC (Full Well Capacity) goes down. What I don't know if this is law of nature or if is possible to make the pixel spacing smaller and maintain FWC? It may be possible by increasing the physical fill factor or by using better dielectrics?

Hi Erik,

AFAIK, the actual conversion/storage of electron charge takes place in a very thin layer (one or two electrons thick). That's why surface area is dominant in determining the per sensel charge storage capacity ("well depth" in CCDs). Actually in CMOS devices the electrons deplete a preset charge but do so at the immediate dielectric boundary of two layers, so the thin layer principle remains dominant.

For many years now, the charge storage capacity has not changed much, and can often be found to be in the 1500 - 1800 electrons per square micron range. I've read some papers a.o. from Dalsa if I'm not mistaken, about attemtps at 'deeper' wells, but I've not seen much change coming out of that yet (with 1800 electrons/micron slowly becoming more mainstream than 1500, which is significant but not revolutionary).

Cheers,
Bart

[ejmartin]

Is it the photosensitive area that is the limiter, or the capacity of the capacitor that accumulates charge during the exposure?  If the former, that would be affected by the decreasing percentage of photosensitive area when photosites are made smaller using a fixed process; if the latter, I don't immediately see why there would be a direct correlation with pixel size.

[Bart_van_der_Wolf]

Is it the photosensitive area that is the limiter, or the capacity of the capacitor that accumulates charge during the exposure?  If the former, that would be affected by the decreasing percentage of photosensitive area when photosites are made smaller using a fixed process; if the latter, I don't immediately see why there would be a direct correlation with pixel size.

Hi Emil,

I agree, but the correlation between saturation point (expressed in no. of Photons or Electrons) and sensel pitch (e.g. converted to square microns surface area), seems staggering. Not that that is rigorous proof of one or the other, just that surface area seems a better predictor than physical layer depth. Layer complexity is larger in CMOS, yet the saturation point seems pretty predictable. But I'd be excited if it wasn't the case. What we could use is literally "deep wells".

Cheers,
Bart

[bjanes]

Hi,

I'm shooting 24.6 MP full frame with a CMOS sensor. With aggressive sharpening I see jaggies on edges. Would I have significantly higher resolution those jaggies would probably go away. That would be oversampling but yield better edges.


So I see benefits of increasing resolution. The problem is that when resolution goes up FWC (Full Well Capacity) goes down. What I don't know if this is law of nature or if is possible to make the pixel spacing smaller and maintain FWC? It may be possible by increasing the physical fill factor or by using better dielectrics?~

Best regards
Erik

Erik,

That is an interesting question; Roger Clark presents some data regarding this issue. See Figures 1 and 10 in his post.The basic problem is that silicon based sensors have an upper limit to charge density (~2000 e-/sq micron); beyond that, blooming (spread of electrons to adjacent pixels) and other problems that are not discussed become problematic. Increasing of the fill factor with gap less pixels and smaller scaled transistors (CMOS) can help, and some progress has been made over the last 10 years. Microlenses and better Bayer array filters can improve quantum efficiency, but do nothing for charge density limitations.

Excellent reviews considering many of these factors are available on the Stanford web site:

How small should pixel size be?
Moore meets Planck and Sommerfeld

Better dielectrics could help with blooming, but I do not know if that is practicable. In the Kodak KAF-40000 product summary, they mention lateral overflow drains are used to suppress blooming, but I would imagine that these might not scale with reduced pixel size.

[bradleygibson]

Interesting discussion, guys.  Thank you for your thoughts and for the links.

[deejjjaaaa]

one or two electrons thick

and Foveon CMOS ?

[Bart_van_der_Wolf]

and Foveon CMOS ?

Dunno. Foveon sensors convert a photon over the course of a micron or 3 tops for visible light, distance 0.1 to 3 micron depending on wavelength 400 nm to 700 nm . How densely are the resulting electrons stored in the doped layer? All I know is that some doped layers are as thin as 0.05 micron or less, much wider than they are deep anyway.

Cheers,
Bart

P.S. Maybe this is useful, http://en.wikipedia.org/wiki/Depletion_layer, although it doesn't give an absolute answer. It's clear though that most of the action takes place extremely close to the P-N junction, which is a very thin "plane".